In order to cover a wide range of power and performance requirements with a single chip, a trend is to embed two processor cores together to offer different balances in different running scenarios. Hence, process migration will happen from one core to another when the running scenario is to be changed. To achieve very fast process migration from one processor core to another, shared register files technique could be used to allow one processor core to access the all process contexts written by another processor core. In this way, the process migration can be achieved with almost no latency and no software cost.
However, since the two cores are targeting different timing and power budgets, it is difficult for the shared register files to meet both of the requirements of the two cores. Normally, one core will be designed for very low power dissipation and is very slow, while another core will be high performance and thus dissipates much more power. Due to the CMOS circuit nature, a very fast circuit will use more area, and thus consume more power; on the contrary, an extremely low power circuit should use the minimum area, but its speed is quite poor.
There is further need for a register file organization for a chip that has a very high performance for the high speed core, while having a very low power requirement for the low power core.